ECE 8893 – Parallel Programming for FPGAs

Instructor: Cong (Callie) Hao

Time: Tue. & Thu., 3:30 PM – 4:20 PM

Course Information

Instructor Office Hour: Tuesday 4:30 PM – 5:30 PM, Klaus 2306
TA: Hanqiu Chen
TA Office Hour: Friday 4:30 PM – 5:30 PM, Klaus 2304

Course Schedule: Here

Labs, final projects, sign-up sheets, and leaderboard: ECE8893 GitHub

Useful Links and Interesting Projects

Xilinx resources (the most helpful resource for this class)
- https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas
- https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Getting-Started-with-Vitis-HLS
A floating-point matrix multiplication using HLS: https://github.com/twaclaw/matmult
A related course (CS 3220) from the CS department taught by Professor Hyesoon Kim: https://gt-cs3220.github.io/
Vitis HLS examples and tutorial
- Introductory examples: https://github.com/Xilinx/Vitis-HLS-Introductory-Examples
  - E.g., Pipeline, interface, dataflow.
- A more comprehensive tutorial: https://github.com/Xilinx/Vitis-Tutorials

Course Overview

FPGAs have been pivotal in delivering low-power, high-throughput, and low-latency solutions across diverse domains. With the explosion of computational demands in AI, big-data processing, and scientific computing, FPGAs have become integral to applications like deep neural networks, graph processing, and bioinformatics. Industry leaders like Amazon (AWS F1), Microsoft (Azure FPGA Cloud), and academic initiatives such as Xilinx’s Adaptive Compute Clusters exemplify the growing adoption of FPGA technology.

This course explores recent advancements in FPGA programming for computation-intensive applications using High-Level Synthesis (HLS). It covers FPGA architectures, key parallel programming techniques, and hands-on design examples in diverse application domains. By adopting behavioral-level programming in C/C++ via HLS tools, learners will boost development productivity and explore algorithm/accelerator co-design as a promising area of research.

Key Highlights

FPGA Development Productivity with HLS: The course emphasizes productivity in FPGA development through behavioral-level programming in C/C++ using modern HLS tools. Learners will explore the advantages of agile development methodologies to quickly prototype and iterate designs.
Practical Examples: Multiple hands-on design examples will be provided, allowing learners to jump-start basic designs with opportunities for further optimization and exploration.
Diverse Application Domains: The course will cover FPGA accelerations in various fields, including but not limited to deep learning, graph processing, and scientific computing, offering a broader perspective on FPGA applications.
Algorithm/Accelerator Co-Design: An optional but highly recommended module will delve into the co-design of algorithms and accelerators, a critical research area for achieving optimal performance in FPGA-based systems.

State-of-the-Art FPGA Programming and Analysis Tools

To provide learners with a competitive edge, the course will introduce a wide range of cutting-edge FPGA programming tools from both academia and industry, subject to availability and course duration:

Programming Tools:
- Vitis HLS (AMD): A commercial HLS tool for FPGA
- Catapult (Siemens): A commercial HLS tool for both FPGA and ASIC
- TAPA (UCLA): A task-parallel programming model for FPGA design
- ALLO (Cornell): A framework for efficient FPGA programming
- XLS (Google): An open-source HLS tool for ASIC
Simulation Tool:
- LightningSim (Georgia Tech): An efficient HLS simulator
Benchmarking Tool:
- HLSFactory (Georgia Tech): An infrastructure to collect and evaluate HLS designs

Syllabus and Outline

Overview of FPGA
1. FPGA architecture
2. FPGA programming tutorial (Vivado)
Overview of High-Level Synthesis (HLS)
1. HLS introduction
2. Vitis HLS tutorial
Overview of Machine Learning
1. Deep Neural Networks, Graph Neural Networks
2. Neuro-symbolic AI (Guest lecturer: Zishen Wan)
FPGA Design Techniques (I)
1. Data precision and model quantization
2. Loop optimizations and array partitioning
3. Data reuse and model tiling
FPGA Design Techniques (II)
1. Storage and memory access
2. Data streaming
3. C/RTL Co-simulation
Other Tools: HLS design, Simulation, and Benchmarking
1. TAPA (UCLA): HLS design tool
2. ALLO (Cornell): HLS design tool
3. XLS (Google): HLS design tool
4. Catapult (Siemens): HLS design tool
5. LightningSim: fast HLS simulation tool
6. HLSFactory: HLS benchmark infrastructure

Course Grading

Lab Assignments: 30% (3 Labs – 10% each)
Paper Presentation: 10%
Final Project: 60%
- Mid-term Report: 5%
- Final Report (with correct performance numbers): 20%
- Source Code: 25% — must be submitted to HLSFactory
- Presentation: 10%

Course Policies

Attendance and Absence. Students are expected to attend all lectures and exams. If one has a documented emergency or a university-mandated reason, get in touch with the instructor before (preferable) or latest by the day of the exam.

Learning Accommodations. If needed, we will make classroom accommodations for students with disabilities. These accommodations should be arranged in advance and in accordance with the Office of Disability Services (http://www.adapts.gatech.edu)

Honor Code. Students are expected to abide by the Georgia Tech Academic Honor Code (http://www.policylibrary.gatech.edu/student-affairs/academic-honor-code). Honest and ethical behavior is always expected. All incidents of suspected dishonesty will be reported to and handled by the office of student affairs. Students will have to do all assignments individually unless explicitly told otherwise. Students may discuss with classmates but may not cop