Exploring the power of GNN and RL in EDA
This project explores the power of graph neural network (GNN) and reinforcement learning (RL) in the EDA area: high-level synthesis, specifically. GPP is a highly accurate graph-neural network-based performance and resource predictor; RLMD is a reinforcement-learning-based multi-objective DSE engine for resource allocation; CT is a code transformer that extracts the data flow graph from original HLS C/C++ and generates synthesizable code with new HLS directives.
- [Publications] Some amazing results can be found in this paper – IronMan. It wins the best paper award in GLSVLSI’2021.
- [Ongoing] We’re exploring the power of GNNs in broader applications in EDA — accuracy prediction for approximate computing, circuit quality prediction, logic synthesis, etc.
Domain-Specific Accelerators on FPGA
FPGAs are good platforms for domain-specific applications. We’re generally interested in accelerating “almost” everything on FPGA as long as it’s necessary: DNNs, GNNs (both training and inference), graph computations, etc. Especially we’re building GNN accelerators on FPGA, which is of great importance for scientific computing.
- Bit-level: low-loss low-bit data quantization techniques.
- Module-level: high efficiency computing unit, i.e., IP cores on FPGA. Such IPs are open-sourced and are written in C, which can be synthesized using HLS tools.
- Architecture-level: a fine-grained, tile-based low-latency FPGA accelerator.
- [Ongoing] GNN accelerators on FPGA and let’s automate it!
NAIS: Neural Architecture and Implementation Search
This project focuses on a novel co-search methodology beyond NAS (neural architecture search), called NAIS – neural architecture and implementation search. NAIS incorporates hardware implementation search into NAS to produce hardware-efficient AI algorithms as well as optimized hardware implementations, within limited hardware resource and performance constraints.
Graph-based Computation Acceleration
This project focuses on sw/hw co-design for graph-based computation and processing, such as graph neural network and graph algorithms (pagerank, recommender system, etc.), for acceleration, memory reduction, or energy reduction.
- [Publications] DAC’21
- [Ongoing] We’re developing interesting GNN accelerators on FPGA! This is of great importance and largely beneficial to scientific computing.
- [Ongoing] We are exploring more optimization opportunities of acceleration and memory reduction through both algorithm and dedicated hardware architecture.
HLS: High-Level Synthesis for Agile EDA
High-Level Synthesis (HLS) is an automated design process that interprets an algorithmic description (C, C++, SystemC, etc.) of the desired behavior and creates digital hardware (VHDL, Verilog, etc.) that implements that behavior [ref]. HLS greatly boosts productivity for hardware development such as ASIC and FPGA design. Our main research interests include:
- [Past] Traditional HLS: core algorithms such as operation scheduling and functional unit and register binding.
- [Ongoing] Modern HLS: domain-specific (machine learning, graph processing) HLS, HLS for heterogeneous platforms, etc. HLS design space exploration: to further alleviate human efforts
- [Ongoing] We are exploring HLS for agile development and analog design automation. This is game-changing for analog/mixed-signal development!
ML Algorithm and System for Autonomous Driving
We proposed a hybrid GPU + FPGA platform for autonomous driving cars, which introduces redundancy into the system for reliability: the FPGA system acts as a fallback system when GPU failure occurs. In addition, hardware heterogeneity decouples the development of the main driving task and safe-mode driving task, as well as the development of GPU and FPGA algorithms.
We’re also working on 2D/3D object detection for autonomous driving ith/without lidar sensors.